A DRAM cell typically includes a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor that are built in or on a semiconductor silicon substrate. As semiconductor integration continues to increase, device dimensions are necessarily decreased accordingly so as to all manufacture of DRAM devices with larger memory capacities and higher processing speeds.
Because three-dimensional (3D) capacitor structures are being made smaller and smaller, and therefore occupying smaller areas of the semiconductor substrate, the 3D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAMs of 64 megabytes and above. However, for a conventional DRAM cell, although the capacitor has been designed in three dimensions, the transistor is still designed in two dimensions, and the transistor covers quite a few areas of the semiconductor substrate and cannot satisfy the need for high integration. Therefore the integration of DRAM cell array is limited.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.